Integrating nanotechnology with silicon wafer technology

Using a spin-on coating that is applied to a silicon wafer, nanotech researchers have developed a method for mass fabrication of nanowire photonic and electronic devices. From Harvard University, via AAAS EurekAlert, “Scientists demonstrate method for integrating nanowire devices directly onto silicon“:

Fabrication technique could yield low-cost, scalable nanowire photonic and electronic circuits

Applied scientists at Harvard University in collaboration with researchers from the German universities of Jena, Gottingen, and Bremen, have developed a new technique for fabricating nanowire photonic and electronic integrated circuits that may one day be suitable for high-volume commercial production.

Spearheaded by graduate student Mariano Zimmler and Federico Capasso, Robert L. Wallace Professor of Applied Physics and Vinton Hayes Senior Research Fellow in Electrical Engineering, both of Harvard’s School of Engineering and Applied Sciences (SEAS), and Prof. Carsten Ronning of the University of Jena, the findings will be published in Nano Letters [abstract]. The researchers have filed for U.S. patents covering their invention.

While semiconductor nanowires—rods with an approximate diameter of one-thousandth the width of a human hair—can be easily synthesized in large quantities using inexpensive chemical methods, reliable and controlled strategies for assembling them into functional circuits have posed a major challenge. By incorporating spin-on glass technology, used in Silicon integrated circuits manufacturing, and photolithography, transferring a circuit pattern onto a substrate with light, the team demonstrated a reproducible, high-volume, and low-cost fabrication method for integrating nanowire devices directly onto silicon.

“Because our fabrication technique is independent of the geometrical arrangement of the nanowires on the substrate, we envision further combining the process with one of the several methods already developed for the controlled placement and alignment of nanowires over large areas,” said Capasso. “We believe the marriage of these processes will soon provide the necessary control to enable integrated nanowire photonic circuits in a standard manufacturing setting.”


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