Intel Makes Nano Leap

from the straining-for-speed dept.
Gina Miller writes " reports that the Santa Clara, Calif. based Intel Corperation is making plans to 'leap into the nanotechnology era' with a 'strained silicon' technology in which the lattice structure of a silicon wafer is strained to stretch the atoms apart, boosting electric current flow and chip performance and lowering costs. This 90 nm process technology will be used to make transistors with gate lengths less than 50 nanometers, and will be used to produce a chip named 'Prescott' that is schedualed to hit the market towards the end of 2003. Some technical details on the process can be downloaded as a PDF file from the Intel site."

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