from the STM-nano-fabrication dept.
John Faith points out an article in EE Times in which Japanese nanotechnology research scientist Masakazu Aono, head of the surface and interface laboratory at Japan's Institute of Physical and Chemical Research, claims his team is now only months away from developing Japan's first single-electron tunneling transistor capable of operating at room temperature ("Researchers close in on single-atom switch," by P.Kallender, 7 March 2001).
The transistor Aono is developing consists of three, 3-nanometer-wide "wires" that act as a source and a drain, each separated from a well containing a 10-atom-diameter cluster of 500 silver atoms that acts as a capacitor. On the other side of the separation lies the gate, which sits 4 nm from the capacitor, with the whole unit resting on a graphite substrate. The circuit works by exploiting the difference in the quantum conductance potentials created between the source drain and the capacitor. When carrying a single electron, current can flow through source and drain, said Aono, but 1 volt placed at the gate adds a second electron to the capacitor, thus raising its potential and closing the circuit.
"We can make an atomic switch in a cluster of silver atoms," he said. "The island is so small we are talking about a one-electron effect circuit."
Read more for additional details . . .
From the report in EE Times:
The circuit relies on a series of process technologies built around STM probe manipulation and redevelopment, and the whole project rests on one key breakthrough ó the manufacture of a one-molecule-thick conductor out of an insulator at room temperature. This breakthrough occurred late last year when Aono and a fellow researcher, Yuji Okawa, perfected a technique to create the multiple polydiacetylene channels that can support the flow of current. By applying a tiny voltage probe to a single-molecule-layer of compound monodiacetylene film, they found they could repeatedly produce a domino-effect chain that was one molecule wide but up to 300-nm long ó in effect, a conductive "wire."
The researchers used a single-tungsten-atom-tipped STM probe to punch a 0.3-nm pit in the silicon substrate to create the capacitor well. They are now struggling to perfect the precise carving of a pit to contain the capacitor . . . Then, in an application reminiscent of a fountain pen . . . an STM probe soaked in ionic Ag2S, [is used] to "drip" the atomic-sized silver blobs into the holes to create the cluster capacitor.
By creating a network of wires and pits, Aono is confident the two-man team can create a rudimentary circuit board, recreating the birth of semiconductor integration but on a nanometer scale.
