At the 2005 ISSCC HP and Intel are announcing the Montecito (hmmm… wonder where they got that name…) release of the Itanium microprocessor. Using a 90nm process two dual-threaded 64-bit cores and 26.5 MB of cache add up to a total of 1.72 billion transistors and operating at 2 GHz. Heat production is limited to 100W. Articles here & here. Kind of interesting considering that in 2002 they were predicting that a billion transistor multi-core procesor would require the 65nm process and wouldn't be available until 2007.
More ISSCC news… At the conference IBM, Sony and Toshiba will be discussing its new "cell" chip based on the Power architecture containing 234 million transistors running at 4.6 GHz. The architecture according to some reports has 4 cells each of which is attached to 8 APUs each of which consists of 4 FPUs and 4 IUs. The estimated processing capacity is in the vicinity of 1 Teraop/chip. More news here and here.
Interestingly the Cell processor is well suited for an integrated assembly of thousands of processors to achieve Petaflop computing as is slated for the IBM's BlueGene/P efforts. This would be an ideal architecture for protein folding and applications that require molecular modeling of nanoscale machinery. In addition a Petaflop is about the level where supercomputer computational capacity is seriously equivalent to human brain computational capacity.
Here is further discussion of efforts with respect to Squeezing Supercomputers onto a Chip.
